this post was submitted on 08 Apr 2025
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[โ€“] just_another_person@lemmy.world 3 points 2 weeks ago (1 children)

I don't even think you know what you're trying to say at this point, because it's not making sense. Think what you will, but it's obvious your conception of how computer architecture works is flawed. You'll see this memory in machines and hopefully figure it out though. Good luck ๐Ÿคž

[โ€“] barsoap@lemm.ee 2 points 1 week ago (1 children)

So... what's wrong about my characterisation of computer hardware? Do you have any issue with the claim that RAM doesn't talk directly to the SSD, but via the CPU? If yes, please show me the traces on the motherboard which enable that. About the importance of latency to CPU-type computations?

Or do you want to tell me how it's absolutely unsuspicious to bang out a press release in tech and talk about "speed", not distinguishing between bandwidth and latency? Where's the fucking numbers. There's no judging the tech without numbers and them not being forward with those numbers means they're talking to investors, not techies.

[โ€“] just_another_person@lemmy.world 1 points 1 week ago (1 children)

I'm not even sure where you got this RAM talking to storage thing from. This is why I'm saying you don't know what you're talking about it. I think your fundamental understanding of this is flawed.

[โ€“] barsoap@lemm.ee 1 points 1 week ago (1 children)

It was you who was talking about "bus paths" and "traversing CPU>RAM>SSD". There's neither buses connected up to any of those things nor does the data ever flow like that, it always flows via the CPU.

[โ€“] just_another_person@lemmy.world 1 points 1 week ago (1 children)

๐Ÿคฃ That isn't a relational diagram. Simply pointing out the three bus paths.

[โ€“] barsoap@lemm.ee 0 points 1 week ago

That's three devices. There's two connections between them, and they go "RAM<->CPU<->SSD". The first <-> is the DRAM Phy, the second <-> is 1-4 PCIe lanes. Neither of them are a bus. There is no third connection.