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New 'DRAM+' memory designed to provide DRAM performance with SSD-like storage capabilities, uses FeRAM tech
(www.tomshardware.com)
This is a most excellent place for technology news and articles.
It was you who was talking about "bus paths" and "traversing CPU>RAM>SSD". There's neither buses connected up to any of those things nor does the data ever flow like that, it always flows via the CPU.
๐คฃ That isn't a relational diagram. Simply pointing out the three bus paths.
That's three devices. There's two connections between them, and they go "RAM<->CPU<->SSD". The first <-> is the DRAM Phy, the second <-> is 1-4 PCIe lanes. Neither of them are a bus. There is no third connection.