Technology

59666 readers

3188 users here now

This is a most excellent place for technology news and articles.

Our Rules

Follow the lemmy.world rules.
Only tech related content.
Be excellent to each another!
Mod approved content bots can post up to 10 articles per day.
Threads asking for personal tech support may be deleted.
Politics threads may be removed.
No memes allowed as posts, OK to post as comments.
Only approved bots from the list below, to ask if your bot can be added please contact us.
Check for duplicates before posting, duplicates may be removed

Approved Bots

founded 1 year ago

MODERATORS

705

The Framework Laptop 13 is about to become one of the world’s first RISC-V laptops (www.theverge.com)

submitted 5 months ago by schizoidman@lemmy.ml to c/technology@lemmy.world

119 comments fedilink hide all child comments

you are viewing a single comment's thread
view the rest of the comments

[–] __dev@lemmy.world 2 points 5 months ago

compressed instruction set /= variable-width [...]

Oh for sure, but before the days of super-scalars I don't think the people pushing RISC would have agreed with you. Non-fixed instruction width is prototypically CISC.

For simpler cores it very much does matter, and “simpler core” here can also could mean barely superscalar, but with insane vector width, like one of 1024 GPU cores consisting mostly of APUs, no fancy branch prediction silicon, supporting enough hardware threads to hide latency and keep those APUs saturated. (Yes the RISC-V vector extension has opcodes for gather/scatter in case you’re wondering).

If you can simplify the instruction decoding that's always a benefit - moreso the more cores you have.

Then, last but not least: RISC-V absolutely deserves the name it has because the whole thing started out at Berkeley.

You'll get no disagreement from me on that. Maybe you misunderstood what I meant by "CISC-V would be just as exciting"? I meant that if there was a popular, well designed, open source CISC architecture that was looking to be the eventual future of computing instead of RISC-V then that would be just as exciting as RISC-V is now.